Inverted T-Shaped Tunnel Field-Effect Transistors for Extremely Low Power Chip Applications
Author:
Affiliation:
1. School of Computer and Systems Sciences, Jawaharlal Nehru University,New Delhi,India
2. Swami Shraddhanand College, University of Delhi,New Delhi,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10628446/10628545/10628635.pdf?arnumber=10628635
Reference17 articles.
1. Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric
2. Short-channel effect in fully depleted SOI MOSFETs
3. Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs
4. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors
5. A Review of Tunnel Field-Effect Transistors for Improved ON-State Behaviour
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