The Discussion of the Typical BEOL Design Rules from 3 nm to 2 nm Logic Process with EUV and High NA EUV Lithography-Reference-Cited by-同舟云学术

The Discussion of the Typical BEOL Design Rules from 3 nm to 2 nm Logic Process with EUV and High NA EUV Lithography

Published:2021-12-12 Issue: Volume: Page:
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Container-title:2021 International Workshop on Advanced Patterning Solutions (IWAPS)
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Author:

Wu Qiang,Li Yanli,Zhu Xiaona,Yu Shaofeng

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9670881/9671056/09671251.pdf?arnumber=9671251

Reference5 articles.

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3. A Study of the Advantages to the Photolithography Process brought by the High NA EUV Exposure Tool in Advanced Logic Design Rules;li;Proc IWAPS 2021 IEEE Xplore,0

4. TSMC and IMEC on Advanced Process and Devices Technology Toward 2nm;jones;VLSI Symposium,0

5. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers;subramanian;Proc 2020 Symp On VLSI Technon Digest of Technical Papers- TH3 1,0

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