Process Window, and Process Optimization in Both Low and High Na EUV Processes for Advanced Logic Technologies Nodes
Author:
Affiliation:
1. School of Microelectronics, Fudan University,Shanghai,China,200433
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9856647/9856709/09856929.pdf?arnumber=9856929
Reference7 articles.
1. High-NA EUV lithography enabling Moore’s law in the next decade
2. A Simulation Study for Typical Design Rule Patterns and Stochastic Printing Failures in a 5 nm Logic Process with EUV Lithography
3. A Study of the Advantages to the Photolithography Process brought by the High NA EUV Exposure Tool in Advanced Logic Design Rules
4. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
5. The Discussion of the Typical BEOL Design Rules from 3 nm to 2 nm Logic Process with EUV and High NA EUV Lithography
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