A Precise Wafer Thinning Integration Process for nano-TSV Formation
Author:
Affiliation:
1. Institute of Microelectronics Agency for Science, Technology and Research (A*STAR),Singapore,Singapore
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195393.pdf?arnumber=10195393
Reference12 articles.
1. Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing
2. Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration
3. The advancement of silicon-on-insulator (SOI) devices and their basic properties
4. Impact of Sub-µm Wafer Thinning on Latch-up Risk in STCO Scaling Era
5. IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ- & n- TSVs
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1. Investigation of fracture behaviors in copper influenced by the angle of oblique edge nanocrack;Journal of Materials Science;2024-07-31
2. Electrical Characterization and Reliability Studies of Nano-TSV;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
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