Process Design Kit and Initial Demonstration of Digital Metal-Embedded Chip Assembly for High Density IO Fan-Out Packaging-Reference-Cited by-同舟云学术

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Process Design Kit and Initial Demonstration of Digital Metal-Embedded Chip Assembly for High Density IO Fan-Out Packaging

Published:2023-05 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)
language:
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Author:

Nadri Souheil¹,Tu B-A. Clayton¹,Herrault Florian¹,Sharifi Hasan¹,McCue Jamin²,Khan Abdullah³,Schwan David³,Botticello David³,Das Sanjana³,Kuzmenko Daniel¹,Wong Joel¹,Phan Vu¹,Nguyen Jason¹,Wilt Courtney¹

Affiliation:

1. HRL Laboratories, LLC,Malibu,CA,90265

2. The Air Force Research Laboratory,OH,45433

3. Cadence Design Systems, Inc,San Jose,CA,95134

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195363.pdf?arnumber=10195363

Reference7 articles.

1. 10μm Pitch Bumping of Singulated Die Using a Temporary Metal-Embedded Chip Assembly Process

2. Scaling M-Series™ for Chiplets

3. TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules

4. Heterogeneous Integration Technologies for Next-Generation RF and mm-Wave Subsystems;herrault;Proc CS MANTECH Conf,0

5. Alumina Passives Using the Interconnect Layer of Metal-Embedded Chip Assembly Processing

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