Flip Chip Process Enablement in IC Memory Stacked Die Package
Author:
Affiliation:
1. Micron Memory Taiwan, Co., Ltd.,Taichung City,Taiwan,42152
2. Micron Technology, Inc.,Boise,ID,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195827.pdf?arnumber=10195827
Reference15 articles.
1. Quantifying impact of design parameters on Ultra-Low k ILD reliability in fine pitch Cu bump interconnect structures
2. A Novel Metal Scheme and Bump Array Design Configuration to Enhance Advanced Si Packages CPI Reliability Performance by Using Finite Element Modeling Technique
3. Fine Pitch Cu Pillar with Bond on Lead (BOL) Assembly Challenges for Low Cost and High Performance Flip Chip Package
4. Experimental and numerical investigations on Cu/low-k interconnect reliability during copper pillar shear test
5. Reliability issues on the high speed DRAM flip-chip package using gold stud bump, lead free solder, and underfill;lee;58th IEEE-Electronic Components and Technology Conference,0
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