A Novel Metal Scheme and Bump Array Design Configuration to Enhance Advanced Si Packages CPI Reliability Performance by Using Finite Element Modeling Technique
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8795274/8811008/08811226.pdf?arnumber=8811226
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Novel Stacked-via Cu/ELK Interconnection Design Configuration to Enhance Advanced Si Packages Reliability Performance;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05
2. Flip Chip Process Enablement in IC Memory Stacked Die Package;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05
3. Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method;Electronics;2021-12-25
4. Numerical Model for Understanding Failure Mechanism of Back End of Line (BEOL) in Bump Shear;2020 IEEE 70th Electronic Components and Technology Conference (ECTC);2020-06
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