Warpage and RDL Stress Analysis in Large Fan-Out Package with Multi-Chiplet Integration-Reference-Cited by-同舟云学术

Warpage and RDL Stress Analysis in Large Fan-Out Package with Multi-Chiplet Integration

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
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Author:

Wong Jen-Hsien¹,Wu NanYi¹,Lai Wei-Hong¹,Chen Dao-Long¹,Chen Tang-Yuan¹,Chen Chung-Hao¹,Wu Yi-Hsien¹,Chang Yung-shun¹,Kao Chin-Li¹,Tarng David¹,Chong Lee Teck¹,Hung CP¹

Affiliation:

1. Advanced Semiconductor Engineering Inc.,Corporate R&D Center,Kaohsiung,Taiwan (R.O.C)

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816702.pdf?arnumber=9816702

Reference8 articles.

1. A Comparative Study of 2.5D and Fan-out Chip on Substrate : Chip First and Chip Last

2. Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate

3. Advanced HDFO Packaging Solutions for Chiplets Integration in HPC Application

4. A Production-worthy Fan-Out Solution - ASE FOCoS Chip Last

5. Bimaterial curvature measurements for the CTE of adhesives: optimization, modeling, and stability

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