Dielectric Interface Engineering for High-Performance Monolayer MoS2 Transistors via TaOxInterfacial Layer
Author:
Affiliation:
1. Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
2. Materials Science and Engineering Division, National Institute of Standards and Technology (NIST), Gaithersburg, MD, USA
Funder
Semiconductor Research Corporation (SRC) and National Institute of Standards and Technology (NIST) through the NEW LIMITS Center
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10081247/10068125.pdf?arnumber=10068125
Reference53 articles.
1. The performance limits of hexagonal boron nitride as an insulator for scaled CMOS devices based on two-dimensional materials
2. Insulators for 2D nanoelectronics: the gap to bridge
3. Interface Engineering for High-Performance Top-Gated MoS2Field-Effect Transistors
4. Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning
5. Van der Waals contacts between three-dimensional metals and two-dimensional semiconductors
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3. Near-Ideal Subthreshold Swing in Scaled 2D Transistors: The Critical Role of Monolayer hBN Passivation;IEEE Electron Device Letters;2024-07
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