Effects of the LPCVD Gate Dielectric Deposition Temperature on GaN MOSFET Channels and the Root Causes at the SiO2-GaN-Interface
Author:
Affiliation:
1. Department of Advanced Technologies and Micro Systems, Robert Bosch GmbH, Renningen, Germany
2. Institute for Electrical Drives, Power Electronics and Devices, University of Bremen, Bremen, Germany
Funder
Electronic Component Systems for European Leadership Joint Undertaking
European Union’s Horizon 2020 research and innovation program and Germany, France, Belgium, Austria, Sweden, Spain, Italy
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/16/10457976/10384349.pdf?arnumber=10384349
Reference21 articles.
1. GaN power device for automotive applications;Kachi
2. Control of the inversion-channel MOS properties by Mg doping in homoepitaxial p-GaN layers
3. Mg implantation dose dependence of MOS channel characteristics in GaN double-implanted MOSFETs
4. Demonstration of 1200 V/1.4 mΩ cm2 vertical GaN planar MOSFET fabricated by an all ion implantation process
5. LPCVD against PECVD for micromechanical applications
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1. Experimental and Numerical Analysis of Off-State Bias Induced Instabilities in Vertical GaN-on-Si Trench MOSFETs;IEEE Transactions on Power Electronics;2024-11
2. SiO2‐GaN Interface Improvement by Wet Cleaning and In Situ Annealing for GaN MOS Transistors;physica status solidi (a);2024-07
3. Enhanced field-effect mobility (>250 cm2/V·s) in GaN MOSFETs with deposited gate oxides via mist CVD;Applied Physics Express;2024-06-01
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