Performance and Short-Circuit Reliability of SiC MOSFETs With Enhanced JFET Doping Design

Author:

Lin Chaobiao1,Ren Na1ORCID,Xu Hongyi1ORCID,Sheng Kuang1ORCID

Affiliation:

1. College of Electrical Engineering, Zhejiang University, Hangzhou, China

Funder

National Natural Science Foundation of China Youth Fund

“Pioneer” R&D Program of Zhejiang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Characteristics and avalanche investigation of SiC VDMOSFETs with enhanced P-Based implantation;Microelectronics Reliability;2024-09

2. A novel SiC VD-MOSFET with optimized P-type shielding structure in JFET region for improved short circuit robustness;Engineering Research Express;2024-08-22

3. Study on Characteristics and UIS of Hexagonal Planar SiC VDMOSFETs With Varied JFET Width;IEEE Transactions on Device and Materials Reliability;2024-06

4. A Novel SiC Trench MOSFET with Self-Aligned N-Type Ion Implantation Technique;Micromachines;2023-12-07

5. Demonstration of a 1200V Periodic Full-P Encapsulated 4H-SiC Trench MOSFET;2023 20th China International Forum on Solid State Lighting & 2023 9th International Forum on Wide Bandgap Semiconductors (SSLCHINA: IFWS);2023-11-27

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