A novel SiC VD-MOSFET with optimized P-type shielding structure in JFET region for improved short circuit robustness

Abstract

Abstract This paper investigates the short-circuit characteristics of Silicon Carbide (SiC) Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistor (VD-MOSFET) utilizing TCAD tools. Expanding upon the conventional VD-MOSFET structure, a novel 900 V SiC VD-MOSFET with two P-type shielding layers introduced in JFET region (PW-MOSFET), is proposed and designed. In contrast to the traditional VD-MOSFET, PW-MOSFET not only significantly improves short-circuit (SC) reliability but also optimizes static performance. Simulation results reveal that PW-MOSFET demonstrates notably superior SC performance at a DC link voltage of 600 V compared to the traditional VDMOSFET, with a 63% increase in Short-Circuit Withstand Time (SCWT) and a 25% enhancement in Baliga Figure of Merit (FOM). The key factor contributing to this performance enhancement is attributed to the advantageous role of the P-type shielding layers, facilitating adjustments in the current flow path, thereby suppressing saturation current and enhancing the reliability of short-circuit events. Furthermore, the issue of increased characteristic on-state resistance (Ron,sp) resulting from the introduction of the P-type shielding layers is addressed by augmenting the doping concentration in the JFET region.