Device Design Direction of CSTBT for Low Loss and EMI Noise-Reference-Cited by-同舟云学术

Device Design Direction of CSTBT for Low Loss and EMI Noise

Published:2023-12 Issue:12 Volume:70 Page:6144-6150
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Nishi Koichi¹,Konishi Kazuya²^ORCID,Tadakuma Toshiya¹,Furukawa Akihiko¹,Saito Wataru³^ORCID

Affiliation:

1. Power Device Works, Mitsubishi Electric Corporation, Fukuoka, Japan

2. Advanced Technology Research and Development Center, Mitsubishi Electric Corporation, Hyogo, Japan

3. Research Institute for Applied Mechanics, Kyushu University, Fukuoka, Japan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10328902/10304284.pdf?arnumber=10304284

Reference18 articles.

1. A Novel CSTBT with Hole Barrier for High $dV/dt$ Controllability and Low EMI Noise

2. A novel carrier accumulating structure for 1200 V IGBTs without negative capacitance and decreasing breakdown-voltage;rahman;Proc IEEE 30th Int Symp Power Semiconductor Devices ICs (ISPSD),2018

3. CSTBT™ based Split-Gate RC-IGBT with Low Loss and EMI Noise

4. Alternated Trench-Gate IGBT for Low Loss and Suppressing Negative Gate Capacitance

5. Experimental demonstration of the active trench layout tuned 1200 V CSTBT for lower dV/dt surge and turn-on switching loss;konishi;Proc 5th Int Symp Power Semiconductor Devices and ICs (ISPSD),2016

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Split-Gate CSTBT™ for Suppression of Negative Gate Capacitance Under Short Circuit;2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2024-06-02