Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs
Author:
Affiliation:
1. Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10053598/10032272.pdf?arnumber=10032272
Reference38 articles.
1. Sacrificial etching of AlxGa1-xAs for III–V MEMS surface micromachining
2. Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application
3. Stacked Ge Nanosheet GAAFETs Fabrication and Strain Effects Measurement
4. First stacked Ge0.88Sn0.12 pGAAFETs with cap, LG=40 nm, compressive strain of 3.3%, and high S/D doping by CVD epitaxy featuring record ION of 58?A at VOV=VDS=?0.5V, record Gm,max of 172?S at VDS=?0.5 V, and low noise;huang;IEDM Tech Dig,2019
5. Monolithically Cointegrated Tensile Strained Germanium and InxGa1-xAs FinFETs for Tunable CMOS Logic
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1. Lattice Matched Tunable Wavelength GeSn Quantum Well Laser Architecture: Theoretical Investigation;IEEE Journal of Selected Topics in Quantum Electronics;2025-01
2. Ge-Channel Nanosheet FinFETs for Nanoscale Mixed Signal Application;Nanoelectronic Devices and Applications;2024-06-26
3. Enhancing Radio Frequency Performance of InGaAs-SOI-FinFET Through Optimized Channel Doping Density;2024 International Conference on Communication, Computer Sciences and Engineering (IC3SE);2024-05-09
4. GeSn-on-GaAs with photoconductive carrier lifetime >400 ns: role of substrate orientation and atomistic simulation;Nanoscale;2024
5. High-κ Gate Dielectric on Tunable Tensile Strained Germanium Heterogeneously Integrated on Silicon: Role of Strain, Process, and Interface States;ACS Applied Electronic Materials;2023-08-17
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