Analysis of Airgaps for OFF-State Capacitance Reduction in SOI-CMOS RF Switches
Author:
Affiliation:
1. STMicroelectronics, Crolles, France
2. Univ. Lille, CNRS, Univ. Polytechnique Hauts-de-France, JUNIA, UMR 8520-IEMN-Institut d’Electronique, de Microélectronique et de Nanotechnologie, Lille, France
Funder
STMicroelectronics–Institut d’Electronique, de Microélectronique et de Nanotechnologie (IEMN) Joint Laboratory
French Government through the National Research Agency (ANR) through Program Projet d’Investissement d’Avenir (PIA) Equipment of Excellence (EQUIPEX) Laser Processing Platform for Functional Packaging
French RENATECH Network on Micro and Nanotechnologies
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10294316/10255670.pdf?arnumber=10255670
Reference23 articles.
1. Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits
2. A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped inter-connects, self-aligned double patterning and a 0.0588 ?m2 SRAMcell size;natarajan;IEDM Tech Dig,2014
3. Substrate-Induced Dissipative and Non-Linear Effects in RF Switches: Probing Ultimate Performance Based on Laser-Machined Membrane Suspension
4. Air-Gap Technology With a Large Void-Fraction for Global Interconnect Delay Reduction
5. Development of air-gap etching process by a mask approach for characterization of intralayer and interlayer capacitances
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