Analysis of Airgaps for OFF-State Capacitance Reduction in SOI-CMOS RF Switches

Author:

Gheysens Daniel1ORCID,Fleury Alain1ORCID,Monfray Stéphane1,Gianesello Frédéric1,Cathelin Philippe1,Troadec David2,Robillard Jean François2,Dubois Emmanuel2ORCID

Affiliation:

1. STMicroelectronics, Crolles, France

2. Univ. Lille, CNRS, Univ. Polytechnique Hauts-de-France, JUNIA, UMR 8520-IEMN-Institut d’Electronique, de Microélectronique et de Nanotechnologie, Lille, France

Funder

STMicroelectronics–Institut d’Electronique, de Microélectronique et de Nanotechnologie (IEMN) Joint Laboratory

French Government through the National Research Agency (ANR) through Program Projet d’Investissement d’Avenir (PIA) Equipment of Excellence (EQUIPEX) Laser Processing Platform for Functional Packaging

French RENATECH Network on Micro and Nanotechnologies

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

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