An Adaptive Equalizer for 56 Gb/s Duo-Binary SerDes-Reference-Cited by-同舟云学术

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An Adaptive Equalizer for 56 Gb/s Duo-Binary SerDes

Published:2022-10-28 Issue: Volume: Page:
ISSN:
Container-title:2022 7th International Conference on Integrated Circuits and Microsystems (ICICM)
language:
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Author:

Hu Xiaoyue¹,Zhang Jin¹,Lv Fangxu²,Wang Zheng³

Affiliation:

1. Changsha University of Science & Technology,School of Computer and Communication Engineering,Changsha,China

2. National University of Defense Technology,School of Computer Science,Changsha,China

3. Air Force Engineering University,Air and Missile Defense College,Xi’an,China

Funder

National Natural Science Foundation of China

Natural Science Foundation of Hunan Province

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011321.pdf?arnumber=10011321

Reference12 articles.

1. A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET

2. Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

3. Local convergence of the steepest descent method in Hilbert spaces

4. A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

5. 6.2 A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss

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