A Low BER DB-PAM4 Adaptive Equalizer For Large Channel Loss In Wireline Receiver
Author:
Affiliation:
1. Air Force Engineering University,Graduate School,Xi’an,China
2. National University of Defense Technology,School of Computer,Chang’sha,China
3. Air Force Engineering University,Air and Missile Defense School,Xi’an,China
Funder
China Postdoctoral Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011277.pdf?arnumber=10011277
Reference13 articles.
1. A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference
2. FPGA implementation of LMS self correcting adaptive filter (SCAF) and hardware analysis
3. 112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels
4. 6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET
5. 112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels
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