A Novel FinFET Device with a Four-Period Vertically Stacked SiGe/Si Fin
Author:
Affiliation:
1. Integrated Circuit Advanced Process Center Institute of Microelectronics, Chinese Academy of Sciences,Beijing,China
Funder
Beijing Municipal Natural Science Foundation
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011275.pdf?arnumber=10011275
Reference19 articles.
1. Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces
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3. Sulfur passivation for the formation of Si-terminated Al2O3/SiGe(0 0 1) interfaces
4. Selective GeO x-scavenging from interfacial layer on Si 1– x Ge x channel for high mobility Si/Si 1– x Ge x CMOS application;lee;2016 IEEE Symposium on VLSI Technology,2016
5. Investigation on thermal stability of Si0. 7Ge0. 3/Si stacked multilayer for gate-all-around MOSFETS;cheng;Semicond Sci Technol,2020
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