Enhanced low-power high-speed adder for error-tolerant application

Author:

Zhu Ning,Goh Wang Ling,Wang Gang,Yeo Kiat Seng

Publisher

IEEE

Cited by 81 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. HEAD: High-Speed Approximate HEterogeneous ADder for Error-Resilient Applications;Journal of Circuits, Systems and Computers;2024-08-31

2. Design and Analysis of High Performance Heterogeneous Block-based Approximate Adders;ACM Transactions on Embedded Computing Systems;2023-11-09

3. A Comprehensive Model for Efficient Design Space Exploration of Imprecise Computational Blocks;ACM Transactions on Embedded Computing Systems;2023-11-09

4. Synthesis of Approximate Parallel-Prefix Adders;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11

5. Efficient design of approximate adders for FPGAs;2023 International Conference on Research Methodologies in Knowledge Management, Artificial Intelligence and Telecommunication Engineering (RMKMATE);2023-11-01

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