HEAD: High-Speed Approximate HEterogeneous ADder for Error-Resilient Applications

Abstract

Media processing applications can tolerate error up to a certain limit due to the perceptual limitations of the human eye. Since adders are ubiquitous in power-hungry media processing applications, they can be approximated without much compromise in quality. An adder with better error characteristics without significant compromise in area and power is required to meet the future demands of ever-increasing computational needs. In order to achieve the same, a novel segmentation technique has been proposed. By varying the number of bits in each segment, three different designs are proposed, each with its advantage. Each proposed adder is segmented into three portions, namely Most Significant Portion (MSP), Intermediate Significant Portion (ISP) and Least Significant Portion (LSP). The sub-adder’s sum in each portion is computed concurrently to reduce the critical path delay. The proposed heterogeneous adder (HEAD) designs achieve better accuracy than the state-of-the-art designs. Synthesis results show that HEAD consumes less area up to 41.8% and consumes less power ranging from 0.8% to 51%, than existing adders. Exhaustive simulations are carried out on benchmarking image sharpening application to prove that the proposed adders obtain a better quality-effort tradeoff than the existing designs.