Design of Imprecise Multipliers by Using Approximate Technique for Error Resilient Applications

Abstract

Approximate computing is the perfect way for error resilient applications with progress in speed and power but tradeoff with computational accuracy. In this paper, Imprecise Multipliers (IMs) are realized by segregating the partial products into two segments. The most significant bit (MSB) segment is accumulated as per Dadda tree structure and the least significant bit (LSB) segment is accumulated by approximate technique. The proposed Imprecise Multipliers, namely [Formula: see text] and [Formula: see text] are realized using Verilog HDL and simulated using TSMC 65[Formula: see text]nm process. For sake of comparison, the proposed multipliers [Formula: see text] and [Formula: see text] are compared with existing approximate multipliers. From the reported results, it may be noted that [Formula: see text] performs better in terms of area–delay product, power–delay product. While [Formula: see text] achieves a higher peak signal-to-noise ratio (PSNR) among all the multipliers existing in the literature.