Two Mechanisms of Charge Accumulation in Edge Termination of 4H-SiC Diodes Caused by High-Temperature Bias Stress and High-Temperature and High-Humidity Bias Stress
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/8416787/08396839.pdf?arnumber=8396839
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. 3.3 kV 4H-SiC Trench Semi-Superjunction Schottky Diode With Improved ON-State Resistance;IEEE Transactions on Electron Devices;2024-09
2. Experimental and Theoretical Study on failure mechanism of Superjunction MOSFET under H3TRB Testing;2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2024-06-02
3. Dynamic Reverse Bias Test Circuit for SiC MOSFET with Adjustable dV ds/dt;2024 IEEE 10th International Power Electronics and Motion Control Conference (IPEMC2024-ECCE Asia);2024-05-17
4. Analysis of Effects of Defects on Degradation Mechanism of 1200-V/40-A 4H-SiC Junction Barrier Schottky Diodes Induced by High-Reserve Bias Stress;IEEE Transactions on Electron Devices;2024-05
5. Surface Charge Migration in SiC Power MOSFETs Induced by HVDC-H3TRB Testing;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
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