Fast Acquisition Clock and Data Recovery Circuit With Low Jitter-Reference-Cited by-同舟云学术

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Fast Acquisition Clock and Data Recovery Circuit With Low Jitter

Published:2006-05 Issue:5 Volume:41 Page:1016-1024
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zhang R.,La Rue G.S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/34101/01624390.pdf?arnumber=1624390

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. PLL-based clock recovery circuit using ring oscillator;International Journal of Electronics Letters;2015-07-13

2. A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2015-05

3. A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-10

4. Receiver Front-End for 1.25-Gb/s SI-POF;Analog Circuits and Signal Processing;2014-09-23

5. A CMOS 3.2 Gb/s serial link transceiver, using a new PWAM scheme;Analog Integrated Circuits and Signal Processing;2011-09-08

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