A CMOS 3.2 Gb/s serial link transceiver, using a new PWAM scheme-Reference-Cited by-同舟云学术

A CMOS 3.2 Gb/s serial link transceiver, using a new PWAM scheme

Published:2011-09-08 Issue:3 Volume:71 Page:421-432
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Ghaderi Noushin,Hadidi Khayrollah,Khoei Abdollah

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-011-9767-6.pdf

Reference9 articles.

1. Farjad-Rad, R., Yang, C.-K., Horowitz, M. A., & Lee, T. H. (2000). A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver. IEEE Journal of Solid-State Circuits, 35(5), 757–764.

2. Chen, W. H., Dehng, G. K., Chen, J. W., & Liu, S. I. (2001). A CMOS 400-Mb/s serial sink for AS-memory systems using a PWM scheme. IEEE Journal of Solid-State Circuits, 36(10), 1498.

3. Yang, C. Y., & Lee, Y. (2008). A PWM and PAM signaling hybrid technology for serial-link transceivers. IEEE Transactions on Instrumentation and Measurement, 57, 1058–1070.

4. Ghaderi, N., & Hadidi, Kh. (2009). A CMOS 3.2 Gb/s serial link transceiver, using PWM and PAM scheme. In: ECCTD09, European Conference on Circuit Theory and Design, Antalya, Turkey, 23–27 Aug 2009.

5. Razavi, B. (2003). Design of integrated circuits for optical communications. New York: McGraw-Hill.

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