A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor-Reference-Cited by-同舟云学术

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A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor

Published:2014-10 Issue:10 Volume:22 Page:2216-2220
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Li Chung-Yi,Lee Chung-Len,Hu Ming-Hong,Chou Hwai-Pwu

Funder

National Science Council

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/6908070/06656974.pdf?arnumber=6656974

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fast-Locking Phase Locked Loop Dominated by SMC at VCO Voltage Tuning End;IEEE Access;2024

2. A 1-to-3 GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28 nm CMOS;Electronics;2022-06-22

3. PFD with improved average gain and minimal blind zone combined with lock-in detection for fast settling PLLs;Microelectronics Journal;2021-10

4. A 3-6GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28nm CMOS;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

5. CMOS analog and mixed-signal phase-locked loops: An overview;Journal of Semiconductors;2020-11-01

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