A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

Author:

Changsik Yoo ,Kye-Hyun Kyung ,Kyunam Lim ,Hi-Choon Lee ,Joon-Wan Chai ,Nak-Won Heo ,Dong-Jin Lee ,Chang-Hyun Kim

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

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4. Energy Efficient 5Gb/s/pin Baseband Transceiver for 3D Memory Interface;2020 10th Annual Computing and Communication Workshop and Conference (CCWC);2020-01

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