Electrostatic Performance Enhanced in a Dielectric Pocket Junctionless Gate All around MOSFET
Author:
Affiliation:
1. MANIT,Department of ECE,Bhopal,India
2. University of Allahabad,Department of ECE,Prayagraj,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10420829/10420849/10421725.pdf?arnumber=10421725
Reference11 articles.
1. Multiple-gate SOI MOSFETs
2. Subthreshold behavior of triple-gate MOSFETs on SOI material
3. Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review
4. TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET
5. Simulation and analysis of gate engineered triple metal double gate (TM-DG) MOSFET for diminished short channel effects;Gupta;International journal of advanced science and technology,2012
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