Data-flow prescheduling for large instruction windows in out-of-order processors-Reference-Cited by-同舟云学术

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Data-flow prescheduling for large instruction windows in out-of-order processors

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Container-title:Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture
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Author:

Michaud P.,Seznec A.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/7240/19534/00903249.pdf?arnumber=903249

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Efficient Instruction Scheduling Using Real-time Load Delay Tracking;ACM Transactions on Computer Systems;2022-11-24

2. Design and optimization of Issue queue in Out-of-Order superscalar microprocessor;2022 Asia Conference on Algorithms, Computing and Machine Learning (CACML);2022-03

3. Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison;IEICE Transactions on Information and Systems;2022-02-01

4. Design of Low Power Cam Memory Cell for the Next Generation Network Processors;IRO Journal on Sustainable Wireless Systems;2021-12-03

5. Fat Loads: Exploiting Locality Amongst Contemporaneous Load Operations to Optimize Cache Accesses;MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture;2021-10-17

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