Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison

Author:

MATSUDA Yasutaka1,SHIOYA Ryota2,ANDO Hideki1

Affiliation:

1. Department of Information and Communication Engineering, Nagoya University

2. Department of Creative Informatics, Graduate School of Information Science and Technology, The University of Tokyo

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference41 articles.

1. [1] N.H.E. Weste and D.M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, fourth edition, Addition Wesley, 2010.

2. [2] “IEEE international roadmap for devices and systems, 2020 update, more Moore.” https://irds.ieee.org/, 2020.

3. [3] F. Monsieur, E. Vincent, D. Roy, S. Bruyre, G. Pananakakis, and G. Ghibaudo, “Time to breakdown and voltage to breakdown modeling for ultra-thin oxides (Tox<32Å),” Proceedings of the 2001 IEEE International Integrated Reliability Workshop, pp.20-25, Oct. 2001. 10.1109/.2001.993911

4. [4] R. Viswanath, V. Wakharkar, A. Watwe, and V. Lebonheur, “Thermal performance challenges from silicon to systems,” Intel Technology Journal, vol.4, no.3, pp.1-16, Aug. 2000.

5. [5] J. Abella, R. Canal, and A. Gonzalez, “Power- and complexity-aware issue queue designs,” IEEE Micro, vol.23, no.5, pp.50-58, Sept.-Oct. 2003. 10.1109/mm.2003.1240212

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