Design and optimization of Issue queue in Out-of-Order superscalar microprocessor
Author:
Affiliation:
1. College of Computer Science and Technology, National University of Defense Technology,Changsha,Hunan,410073
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9852496/9852487/09852638.pdf?arnumber=9852638
Reference14 articles.
1. Hier-archical Scheduling Windows;brekelbaum;Proceedings of International Symposium on Microarchitecture,0
2. Reducing the complexity of the issue logic
3. A low-complexity issue logic
4. Data-flow prescheduling for large instruction windows in out-of-order processors
5. A Scalable In-struction Queue Design Using Dependence Chains;raasch;pro-ceedings of the 29th International Symposium on Computer Architecture (ISCA02),0
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