A 21.8-41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and −250.3dB FoM-Reference-Cited by-同舟云学术

A 21.8-41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and −250.3dB FoM

Published:2022-06-19 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
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Author:

Chen Wen¹,Shu Yiyang¹,Qian Huizhen Jenny¹,Yin Jun²,Mak Pui-In²,Gao Xiang³,Luo Xun¹

Affiliation:

1. University of Electronic Science and Technology of China,China

2. University of Macau,China

3. Zhejiang University,China

Funder

National Natural Science Foundation of China

Key Basic Research Project of Shenzhen

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9862947/9862948/09863104.pdf?arnumber=9863104

Reference12 articles.

1. Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication

2. A 23.6-38.3GHz low-noise PLL with digital ring oscillator and multi-ratio injection-locked dividers for millimeter-wave sensing;zhang;Proc IEEE Radio Freq Integr Circuits Symp (RFIC),2020

3. A Quadrature Sub-Sampling Phase Detector for Fast-Relocked Sub-Sampling PLL Under External Interference

4. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

5. A Cascaded Mode-Switching Sub-Sampling PLL With Quadrature Dual-Mode Voltage Waveform-Shaping Oscillator

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