Transient Thermal and Electrical Co-Optimization of BEOL Top-Gated ALD In2O3 FETs Toward Monolithic 3-D Integration
Author:
Affiliation:
1. School of Electrical and Computer Engineering and the Birck Nanotechnology Center, Purdue University, West Lafayette, IN, USA
2. Electronics Science and Technology Division, United States Naval Research Laboratory, Washington, DC, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10081247/10018145.pdf?arnumber=10018145
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3. Electrical Characteristics of BEOL-Compatible Top-Gate In2O3 Transistors;2024 IEEE Silicon Nanoelectronics Workshop (SNW);2024-06-15
4. Demonstration of scaling and monolithic stacking for higher integration of integrated circuit using c-axis aligned crystalline oxide semiconductor FET;Japanese Journal of Applied Physics;2024-05-01
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