A low-power pipelined MAC architecture using Baugh-Wooley based multiplier
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7020225/7031081/07031169.pdf?arnumber=7031169
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Approximate Vedic Multiplier Architecture for Efficient CNN Acceleration on Embedded Devices;2024 IEEE 48th Annual Computers, Software, and Applications Conference (COMPSAC);2024-07-02
2. RTL to GDSII Flow Implementation of 8-bit Baugh-Wooley Multiplier;2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO);2022-04-28
3. An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation;Computers, Materials & Continua;2022
4. Application of ameliorated Harris Hawks optimizer for designing of low-power signed floating-point MAC architecture;Neural Computing and Applications;2021-01-16
5. Comparative Review of MAC Architectures;Soft Computing for Intelligent Systems;2021
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