Author:
Liao Yuan-Hsin,Li Gwo-Long,Chang Tian-Sheuan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Media Technology
Cited by
6 articles.
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1. A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC;IEEE Transactions on Circuits and Systems for Video Technology;2018-02
2. Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2017
3. 4K Real-Time HEVC Decoder on an FPGA;IEEE Transactions on Circuits and Systems for Video Technology;2016-01
4. A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-Tier Applications;IEEE Transactions on Circuits and Systems for Video Technology;2015-05
5. High-efficiency pipeline design of binary arithmetic encoder;Science China Information Sciences;2014-01-08