Author:
Song Rui,Cui HongFei,Li YunSong,Wu ChengKe
Publisher
Springer Science and Business Media LLC
Reference12 articles.
1. Lei S F, Lo C C, Kuo C C, et al. Low-power context-based adaptive binary arithmetic encoder using an embedded cache. IET Image Process, 2012, 6: 309–317
2. Liao Y H, Li G L, Chang T S. A highly efficient VLSI architecture for H.264/AVC level 5.1 CABAC decoder. IEEE Trans Circ Syst Video Technol, 2012, 22: 272–281
3. Wang Y S, Liu L B, Yin S Y, et al. Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. Sci China Inf Sci, 2013, 56: 112401
4. Chi C C, Juurlink B. A QHD-capable parallel H.264 decoder. In: Proceedings of International Conference on Super computing. New York: ACM, 2011. 317–326
5. Zhang Y D, Yan C G, Dai F, et al. Efficient parallel framework for H.264/AVC deblocking filter on many-core platform. IEEE Trans Multimedia, 2012, 14: 510–524
Cited by
16 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献