Author:
Dave Omkar,Yadav Deepak Singh,Kothari Jay,Jayakrishnan P.
Cited by
4 articles.
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1. Design and Implementation of a Low Power Arithmetic and Logic Unit for MIPS32 Processor;2024 Third International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2024-04-26
2. Design and Implementation of Optimized Based 32-Bit Arithmetic and Logical Unit;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01
3. Five Stage Pipelined MIPS Processor Verification Interface and Test Module using UVM;2023 International Conference on Sustainable Computing and Smart Systems (ICSCSS);2023-06-14
4. 8-Bit Asynchronous Wave-Pipelined Arithmetic Logic Unit;Nanoelectronic Materials and Devices;2017-11-28