1. Dorojevets, M., Ayala, C., and Kasperek, A. 2009. Development and evaluation of design techniques for high-performance wave-pipelined wide datapath RSFQ processors. In Proceedings of the 12th internationl superconductive electronics conference (ISEC’09), Fukuoka, Japan, June 16–19, 2009.
2. Burleson, Wayne P., Maciej Ciesielski, and Fabian Klass. 1998. Wave-pipelining: a tutorial and research survey. IEEE Transaction on Very Large Scale Integration (VLSI) Systems 6 (3).
3. Parhi, Keshab K. VLSI digital signal processing systems, design and implementation, 690.
4. Kornerup, Peter, David W. Matula. 1987. A bit-serial arithmetic unit for rational arithmetic. In 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).
5. Hyde, P.D., and G. Russell. 2004. A comparative study of the design of synchronous and asynchronous self-checking RISC processors. In Proceedings of 10th IEEE international on-line testing symposium, 2004 (IOLTS 2004).