Design and Implementation of a Low Power Arithmetic and Logic Unit for MIPS32 Processor-Reference-Cited by-同舟云学术

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Design and Implementation of a Low Power Arithmetic and Logic Unit for MIPS32 Processor

Published:2024-04-26 Issue: Volume: Page:1-6
ISSN:
Container-title:2024 Third International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)
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Author:

Naik Pavan¹,S K Harshitha¹,Machali Keerti¹,Madhavan Sowmya¹

Affiliation:

1. Nitte Meenakshi Institute of Technology,dept.of ECE,Yelahanka, Bangalore

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10548017/10548035/10548593.pdf?arnumber=10548593

Reference15 articles.

1. Design and Implementation of Clock Gated ALU performing 16 bit operations;Kumar;International Journal of Research in Engineering and Application (IJREA),2023

2. ASIC implementation of pipelined ALU

3. Low Power implementation of 32-bit RISC Processor with pipelining;Kulkarni,2022

4. 32 bit Multiplication and Division ALU Design Based on RISC Structure;Kui,2022

5. Clock Gating Based Low Power ALU Design;Devendra;International Journal of Science and Research (IJSR),2022

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