Processor Design in 3D Die-Stacking Technologies

Author:

Loh Gabriel H.,Xie Yuan,Black Bryan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 134 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads;ACM Transactions on Architecture and Code Optimization;2023-12-14

2. Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12

3. Thermal coupling analysis and improved dynamic temperature control algorithm for 3D-LSI;2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC);2023-06-25

4. A Robust Integrated Power Delivery Methodology for 3-D ICs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-03

5. High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-11

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