Synthesis of robust delay-fault-testable circuits: practice

Author:

Devadas S.,Keutzer K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths;21st International Conference on VLSI Design (VLSID 2008);2008

2. An implicit path-delay fault diagnosis methodology;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2003-10

3. Efficient Path Delay Testing Using Scan Justification;ETRI Journal;2003-06-09

4. Timing, Test and Manufacturing Overview;The Best of ICCAD;2003

5. Synthesis of symmetric functions for path-delay fault testability;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2000

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