A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology-Reference-Cited by-同舟云学术

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A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology

Published:2006-06 Issue: Volume: Page:
ISSN:
Container-title:2006 64th Device Research Conference
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Author:

Yoon Jae-man,Lee Kangyoon,Park Seung-bae,Kim Seong-goo,Seo Hyoung-won,Son Young-woong,Kim Bong-soo,Chung Hyun-woo,Lee Choong-ho,Lee Won-sok,Kim Dong-chan,Park Donggun,Lee Wonshik,Ryu Byung-il

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4097500/4079456/04097627.pdf?arnumber=4097627

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Improved Parasitic Capacitance-Predictively Aware DTCO: Enhanced Cell Efficiency With Manufacturability and Scalability for 4F² VCT-Based DRAM;IEEE Transactions on Electron Devices;2024-07

2. Design and analysis of gate all around stacked nanosheet-DRAM for future technology node;Japanese Journal of Applied Physics;2024-01-23

3. Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process;Japanese Journal of Applied Physics;2015-03-13

4. Memory Devices;Lecture Notes in Electrical Engineering;2013

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