Energy-Efficient CNTFET-RRAM Based Ternary Logic Design
Author:
Affiliation:
1. School of ECE, SMVD University,Katra,Jammu and Kashmir,India,182320
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10428120/10428096/10428386.pdf?arnumber=10428386
Reference21 articles.
1. A new method on designing and simulating CNTFET_based ternary gates and arithmetic circuits
2. On modelling and characterization of single electron transistor
3. Parameterized Comparison of Nanotransistors Based on CNT and GNR Materials: Effect of Variation in Gate Oxide Thickness and Dielectric Constant
4. Effect of Chiral Vector on Voltage Transfer Characteristics of CNTFET Inverter
5. A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology;Physica Scripta;2024-05-09
2. Tri-state GNRFET-based fast and energy-efficient ternary multiplier;AEU - International Journal of Electronics and Communications;2024-04
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