A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits

Author:

Moaiyeri Mohammad Hossein12,Mirzaee Reza Faghih2,Doostaregan Akbar2,Navi Keivan13,Hashemipour Omid1

Affiliation:

1. Faculty of Electrical and Computer EngineeringShahid Beheshti UniversityGCTehranIran

2. Nanotechnology and Quantum Computing LaboratoryShahid Beheshti UniversityGCTehranIran

3. Department of Electrical Engineering and Computer ScienceUniversity of CaliforniaIrvineCAUSA

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 87 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology;Physica Scripta;2024-07-22

2. Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime;Current Nanoscience;2024-07

3. Design of Ternary and Quaternary Asynchronous Up/Down Counter using CNTFET;AEU - International Journal of Electronics and Communications;2024-05

4. Energy-Efficient Ternary Multiplier;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

5. Remora Optimized Dynamic Neural Network to Design Low-Power CNTFET Logic Gate Realization with Multiple-Valued Circuits;Electric Power Components and Systems;2024-03-18

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