Author:
Goyal Ratnakar,Shrivastava Sachin,Parameswaran Harindranath,Khurana Parveen
Cited by
9 articles.
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1. An Efficient Statistical Clock Skew Analysis Method for Clock Trees;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. SlewFTA: Functional Timing Analysis Considering Slew Propagation;2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT);2022-04-18
3. Path Delay Under Process Variations;Timing Performance of Nanometer Digital Circuits Under Process Variations;2018
4. Gate Delay Under Process Variations;Timing Performance of Nanometer Digital Circuits Under Process Variations;2018
5. Generation and use of statistical timing macro-models considering slew and load variability;Proceedings of the 35th International Conference on Computer-Aided Design;2016-11-07