An Optimal Design Methodology for Yield-Improved and Low-Power Pipelined ADC-Reference-Cited by-同舟云学术

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An Optimal Design Methodology for Yield-Improved and Low-Power Pipelined ADC

Published:2018-02 Issue:1 Volume:31 Page:130-135
ISSN:0894-6507
Container-title:IEEE Transactions on Semiconductor Manufacturing
language:
Short-container-title:IEEE Trans. Semicond. Manufact.

Author:

Mirzaie Nahid^ORCID,Byun Gyung-Su

Funder

NSF CAREER

NSF Grant

SRC

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://ieeexplore.ieee.org/ielaam/66/8270722/8107589-aam.pdf

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms;IET Computers & Digital Techniques;2022-09

2. A VLSI design of clock gated technique based ADC lock-in amplifier;International Journal of System Assurance Engineering and Management;2022-07-30

3. Yield constrained automated design algorithm for power optimized pipeline ADC;Integration;2020-09

4. A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-09

5. Digital Calibration of Elements Mismatch in Multirate Predictive SAR ADCs;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-12

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