Boosting Microprocessor Efficiency: Circuit- and Workload-Aware Assessment of Timing Errors-Reference-Cited by-同舟云学术

Boosting Microprocessor Efficiency: Circuit- and Workload-Aware Assessment of Timing Errors

Published:2021-11 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Symposium on Workload Characterization (IISWC)
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Author:

Tsiokanos Ioannis,Papadimitriou George,Gizopoulos Dimitris,Karakonstantis Georgios

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9668193/9668275/09668276.pdf?arnumber=9668276

Reference88 articles.

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3. Compiler-guided instruction-level clock scheduling for timing speculative processors;fan;2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) DAC,0

4. Slack redistribution for graceful degradation under voltage overscaling

5. DEFCON: generating and detecting failure-prone instruction sequences via stochastic search;tsiokanos;DATE,2020

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