An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor-Reference-Cited by-同舟云学术

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An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor

Published:2019-08 Issue:8 Volume:54 Page:2327-2338
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Jia Tianyu^ORCID,Joseph Russ,Gu Jie^ORCID

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielaam/4/8769979/8716516-aam.pdf

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Dynamic Timing Enhanced Computing for Microprocessor and Deep Learning Accelerators;Artificial Intelligence;2023-11-03

2. A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-11

3. An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC–DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2023-11

4. FLC-EDC: A Fast Low-Cost Error Detection and Correction Scheme for AVFS System Based on Flip-Flops Resampling in 28nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2023

5. Adaptive Clock Management of HLS-generated Circuits on FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2022-12-14

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