LDMOS implementation by large tilt implant in 0.6 μm BCD5 process, flash memory compatible
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx3/3746/10945/00509452.pdf?arnumber=509452
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Ultra low Rdson LDMOS with 12V BVDSS;2022 IEEE International Conference on Semiconductor Electronics (ICSE);2022-08-15
2. Hot Carrier Degradation in a Class of Radio Frequency n-Channel LDMOS Transistors;2006 IEEE International Reliability Physics Symposium Proceedings;2006-03
3. Impact of large angle tilt implantation on the threshold voltages of LDMOS transistors on SOI;Materials Science and Engineering: B;2005-12
4. Automatic 2-D and 3-D simulation of parasitic structures in smart-power integrated circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2002-07
5. Avalanche injection of hot holes in the gate oxide of LDMOS transistors;Solid-State Electronics;2000-07
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