A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/6558851/06508848.pdf?arnumber=6508848
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces;IEEE Journal of Solid-State Circuits;2024-04
2. A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-01
3. A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process;IEICE Electronics Express;2021-09-25
4. A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-06
5. A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-03
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