A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces
Author:
Affiliation:
1. Department of Electrical Engineering, Korea University, Seoul, South Korea
2. Foundry Division, Samsung Electronics, Hwaseong, South Korea
3. Department of Semiconductor System Engineering, Korea University, Seoul, South Korea
Funder
Institute of Information and Communication Technology Planning and Evaluation
Korean Government (MSIT)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/4/10480871/10426764.pdf?arnumber=10426764
Reference15 articles.
1. Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme
2. Recent Evolution in the DRAM Interface: Mile-Markers Along Memory Lane
3. A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel
4. A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
5. A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking
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